The present invention relates to a semiconductor device and a method for fabricating the same, more specifically, a semiconductor device having the interconnection buried in the inter-layer insulating film formed by the dual damascene process, and a method for fabricating the semiconductor device.
As semiconductor devices are larger scaled and more integrated, the design rule of the interconnections are more diminished as the generations advance. Conventionally, the interconnections are formed by depositing interconnection materials and patterning the interconnection materials by lithography and dry etching. As the generations advance, however, this technique has found technical limitations. As a new process which takes place the conventional process for forming the interconnections, a technique called the damascene process, in which trench patterns and hole patterns are formed in the inter-layer insulating film, and interconnection materials are buried in the trenches and holes, is being used. The damascene process makes it easy to form the interconnections of low resistance materials, such as copper, etc., which are difficult to etch by reactive ion etching and is very effective to form low resistance interconnections having downsized patterns.
The damascene process contains the single damascene process, in which via-holes and interconnection trenches are buried separately from each other, and the dual damascene processing, in which via-holes and interconnection trenches are buried concurrently with each other. The dual damascene process, in which via-holes and interconnection trenches are buried by one process, has an advantage of making the fabricating method simpler than the single damascene process.
The methods of forming interconnections by the dual damascene process are described in, e.g., Reference 1 (Japanese published unexamined patent application No. 2000-043419) and Reference 2 (Japanese published unexamined patent application No. 2003-197738). The other related arts are disclosed in, e.g., Reference 3 (Japanese published unexamined patent application No. Hei 05-218209).
However, as devices are more downsized, and the via-holes and the interconnection trenches are smaller-sized, the deposition of barrier metal and plating copper film in the via-holes become difficult. Resultantly, filling defects, such as voids, etc., are often made in the interconnections, which lower the interconnection reliability.